Search - manchester vhdl

[Other resource] Manchester

Description: 基于FPGA/CPLD，采用VHDL语言的曼彻斯特的编解码实现。还包含曼彻斯特码的说明文档。
Platform: | Size: 175256 | Author: 周水斌 | Hits:

[VHDL-FPGA-Verilog] manchester_verilog

Description: 这时manchesite编码，VERILOG语言，VHDL的找本站我发的帖子-manchesite time coding, VERILOG language, VHDL I find a site in a posting
Platform: | Size: 9216 | Author: 李无志 | Hits:

[VHDL-FPGA-Verilog] 曼彻斯特编解码 Xilinx提供_vhdl

Description: 曼彻斯特编解码 Xilinx提供的VHDL的源代码-Manchester codec Xilinx provide VHDL source code
Platform: | Size: 10240 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] manchesterforvhdl

Description: 这是一个曼彻斯特编解码的VHDL源代码，非常好，值得一看。-Manchester codec VHDL source code, a very good eye-catcher.
Platform: | Size: 10240 | Author: 赵云 | Hits:

[VHDL-FPGA-Verilog] 200632814181169853

Description: 曼彻斯特编解码~VHDL?
Platform: | Size: 10240 | Author: www | Hits:

[Other] manchesterdecoder

Description: 曼彻斯特解码程序，用VHDL语言编写，和编码程序配套使用-Manchester decoding procedures, using VHDL language, and coding procedures for supporting the use of
Platform: | Size: 1024 | Author: 万芳 | Hits:

[VHDL-FPGA-Verilog] Manchester

Description: 基于FPGA/CPLD，采用VHDL语言的曼彻斯特的编解码实现。还包含曼彻斯特码的说明文档。-Based on FPGA/CPLD, using VHDL language codec Manchester realize. Manchester code also includes documentation.
Platform: | Size: 175104 | Author: 周水斌 | Hits:

[VHDL-FPGA-Verilog] NRZ_2_Manchester

Description: NRZ码到Manchester转换器 verilog-NRZ code to Verilog converter Manchester
Platform: | Size: 1024 | Author: leysion | Hits:

[VHDL-FPGA-Verilog] mancheester_v

Description: 用Verilog HDL实现的曼彻斯特编码器和解码器。-Using Verilog HDL realize the Manchester encoder and decoder.
Platform: | Size: 9216 | Author: wangyunshann | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 曼彻斯特编码的VHDL源程序?
Platform: | Size: 10240 | Author: weqeqwe | Hits:

[source in ebook] 200681556499797

Description: 曼彻斯特编解码用vhdl编写的，经过quartus功能仿真测试过了的-Manchester codec prepared using VHDL, the Quartus functional simulation has been tested
Platform: | Size: 103424 | Author: yin | Hits:

[File Format] Manchester

Description: “Manchester码（双相码）编码器- Manchester Code (two-phase code) encoder
Platform: | Size: 1024 | Author: 冯小晶 | Hits:

[VHDL-FPGA-Verilog] BFL_Encode

Description: 将宽度为width位的并行输入数据按BiΦ-L码(曼彻斯特码)方式进行编码后串行输出，输出数据的宽度为(2*width)，BiΦ-L码是PCM码的一种，常用的PCM编码方式有：NRZ-L,BiΦ-L和BiΦ-M三种-The width of the parallel-bit width input data by BiΦ-L code (Manchester code) way encoded serial output, the output data width (2* width), BiΦ-L code is a PCM code, commonly used Has PCM encoding: NRZ-L, BiΦ-L and three BiΦ-M
Platform: | Size: 1024 | Author: 贺明辉 | Hits:

[VHDL-FPGA-Verilog] machester_VHDL

Description: manchester码在通信领域中用途广泛这个VHDL程序包括曼彻斯特码的打包和解包。。很难得哦-manchester code in the communications area of a wide range of uses of this process includes the VHDL code packaged Manchester reconciliation package. . Oh, a rare
Platform: | Size: 1024 | Author: 王鹏 | Hits:

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[Other resource] Manchester

[VHDL-FPGA-Verilog] manchester_verilog

[VHDL-FPGA-Verilog] 曼彻斯特编解码 Xilinx提供_vhdl

[VHDL-FPGA-Verilog] manchesterforvhdl

[VHDL-FPGA-Verilog] 200632814181169853

[Other] manchesterdecoder

[VHDL-FPGA-Verilog] Manchester

[VHDL-FPGA-Verilog] NRZ_2_Manchester

[VHDL-FPGA-Verilog] mancheester_v

[VHDL-FPGA-Verilog] VHDL

[source in ebook] 200681556499797

[File Format] Manchester

[VHDL-FPGA-Verilog] BFL_Encode

[VHDL-FPGA-Verilog] machester_VHDL

[VHDL-FPGA-Verilog] md

[VHDL-FPGA-Verilog] md

[Windows Develop] xapp339

[VHDL-FPGA-Verilog] COD_MANCHESTER

[VHDL-FPGA-Verilog] Manchester

[source in ebook] MANCHESTER

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